Electrostatic discharge and electrical overstress account for more than fifty (50) percent of the field related failures in integrated circuits. Accordingly, electrostatic discharge (ESD) and electrical overstress (EOS) protection circuitry plays an important role in the design, layout and testing of integrated circuits (IC) because many of the functional circuit elements on state-of-the-art integrated circuits are susceptible to high voltages caused by, among other things, electrostatic build-up of charge. This is especially true for complementary metal oxide semiconductor (CMOS) based integrated circuits because in high density CMOS circuits, high voltages caused by electrostatic build-up can destroy gate oxides associated with individual transistors and logic gates. To protect against these types of failures, many attempts have been made to develop ESD and EOS protection devices.
One such attempt is disclosed in U.S. Pat. No. 4,692,781 to Rountree et al. entitled Semiconductor Device with Electrostatic Discharge Protection, assigned to Texas Instruments, Inc. The '781 patent discloses an input protection circuit containing a thick-oxide transistor connected between a metal I/O pad and ground. The spacing between the metal-to-silicon drain contact and the channel of this transistor is made large so that the metal drain contact will not be melted by heat propagated along the silicon surface during a current spike caused by an ESD event. U.S. Pat. No. 4,952,994 to Lin entitled Input Protection Arrangement for VLSI Integrated Circuit Devices, assigned to Digital Equipment Corp., also discloses an input protection circuit for diverting electrostatic discharge current away from functional circuit elements which are connected to I/O pads on an integrated circuit chip. The input protection circuit comprises a MOS transistor having a gate electrode and a field oxide insulating layer capable of sustaining high voltages. Other attempts to develop ESD/EOS protection circuits are also disclosed in U.S. Pat. Nos. 5,404,041, 5,450,267 and 5,468,667 to C. H. Diaz, C. Duvvury and S. M. Kang. In particular, the '041 and '667 patents disclose MOS-type ESD/EOS protection devices with source and drain contact spacings that are designed to increase the failure threshold of the protection devices. In addition, the '267 patent discloses an ESD/EOS protection circuit including both MOS and bipolar transistors.
U.S. Pat. No. 5,452,171 to Metz et al. entitled Electrostatic Discharge Protection Circuit for Integrated Circuits, also discloses an ESD protection circuit which uses SCR latch-up current to divert ESD pulse current away from sensitive CMOS circuit structures. The disclosed circuit uses an inverter trigger device, with a voltage divider on its output, to control the amount of voltage necessary to cause latch-up. The disclosed protection circuit also allows the threshold voltage at which latch-up occurs to be adjusted by varying the sizes of the transistors used in the voltage divider.
Notwithstanding these attempts to prevent failures caused by electrostatic discharge and electrical overstress faults using ESD/EOS protection circuits, there continues to be a need for improved electrostatic discharge protection devices.